Context And Mission

The Barcelona Supercomputing Center (BSC) www.bsc.es is embarking on an umbrella of large-scale projects to contribute in the BSCs next generation supercomputer, the Marenostrum 6 (MN6), which will be operational in 2028/2029. In this ambitious and potentially rewarding endeavor, we need engineers and computer scientists at all levels of expertise (from 0 to 20+ years) and in both software and hardware fields. The final team will be around 100 engineers and scientists. The applicants would ideally have experience/ambition in at least one or more of the following fields:

· System software (operating system), including the development of new Linux services, tools, and drivers. Service visualization and containerization. Good understanding of the Linux kernel.
· Compilers, including the development of the LLVM compiler to target new features and/or optimizations (aimed at improving the performance of applications that are currently exploiting the RISC-V ISA).
· Parallel libraries and runtimes, including the development of new features and extensions in parallel library/runtime’s systems for HPC programming models (e.g., MPI, OpenMP, SyCL), and workflow executions (e.g., COMPSs).
· Parallel numerical frameworks, including the use and development of numerical libraries (e.g., BLIS, OpenBLAS), and data analytic frameworks (e.g., Pythorch, Tensor Flow).
· HPC analysis, including the performance analysis of HPC applications, as well as the development of new tools (e.g., Extrae/Paraver) and benchmarks that may help to characterize the system behavior.
· HPC application engineering, including the understanding of actual scientific HPC applications (usually written in C/C++ and Fortran), and the development of modifications/extensions that may improve their performance.
· HPC resource awareness, including a good understanding of the underlying resource utilization and management in terms of nodes, processors, and memory (e.g., Slurm, DLB, Elasticity, DMRLib,…).
· Hardware engineering, including processor architecture and micro-architecture, accelerators, memory hierarchy, memory controllers, HBM, FPGA’s, RTL design, VHDL, verilog, System C, System Verilog, place and route, timing closure, verification, validation, CI, post-silicon debug, DFT, and gate-level simulation

Requirements

Education

Junior profiles: BS or MS in Computer Science, Computer Engineering or Electrical Engineering. Previous industrial experience is a big plus.
Mid-level profiles: PhD in Computer Sciences, Computer Engineering or Electrical Engineering.
Senior profiles: PhD in Computer Sciences, Computer Engineering or Electrical Engineering.

Essential Knowledge and Professional Experience

Junior profiles: Experience in industry is a big plus.
Mid-level profiles: 5+ year experience in industry in a leading role.
Senior profiles: 10-20+ years in industry in a leading role.

Additional Knowledge and Professional Experience

Fluency in English is essential, Spanish is optional (free lessons available after joining)
Opportunity to enroll in Master or PhD program of UPC Computer Architecture Department.

Competences

Planification and Organization
Ability to work individually and in a team
Innovation